Replacement Gate Process
The replacement gate process architecture avoids the problems of work function material stability seen in the gate first architecture. However, the replacement gate architecture requires the insertion of new process modules into the flow, such as CMP. The process is to form a dummy gate structure used to self-align the source and drain implant and anneals, and then strip out the dummy gate materials and replace them with the high-k and metal gate materials. The flow forms an SiO2 or SiON interface between the silicon substrate and the high-k dielectric. A thin protective interfacial layer of metal is then deposited above the dielectric, followed by the temporary polysilicon gate. This is followed by forming the source and drain, salicidation, and depositing the contact etch stop and first inter-layer dielectric. At this point, the polysilicon gates are removed and substantially more metal is added to the interfacial layers to complete the metal gates. There are other variants of the deposition sequence as well.
Although this process is more complex than the gate first technique, proponents claim several advantages. First, separate PMOS and NMOS metals can be used instead of a single metal which is usual for gate first, which allows for greater optimization. In addition, the two metals are not exposed to high temperatures, simplifying material selection. Lastly, the polysilicon gate removal can actually be used to enhance strain techniques thereby increasing drive currents.
The table below shows a simplified outline of the replacement gate process flow, its challenges and the advantages VeraFlex II provides. Click here for information on the gate first process.
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MG = metal gate | WF = work function metal | HK = high-K
Contact ReVera to discuss your specific high-k challenges, and the advantages of the VeraFlex II production metrology system to your production processes.